logic gate
英 [ˈlɒdʒɪk ɡeɪt]
美 [ˈlɑːdʒɪk ɡeɪt]
n. 逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
牛津词典
noun
- 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .
英英释义
noun
- a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
双语例句
- Reversible logic gate cascade is an important part of reversible logic synthesis.
可逆逻辑门级联是可逆逻辑综合的重要组成部分。 - This paper presents the conversion from dynamic logic gate to Markov chain, the solution of dynamic subtree top event failure probability and the method of obtaining the failure mode of subsystem using Markov model, that is sequence cutsets of the dynamic subtree.
论文研究了动态逻辑门向马尔可夫链的转化方法，利用马尔可夫链法求解动态子树顶事件概率，以及通过马尔可夫状态转移图直接找出子系统的故障模式和薄弱环节，即得到动态子树的顺序割集。 - Generally speaking, the video codec in portable system can be realized by two ways: Pure software way of DSP ( digital signal processor) and pure hardware way of ASIC or FPGA ( programmable logic gate array).
一般来说视频编解码器在便携式系统上的实现有以下两种方式：纯软件的DSP（数字信号处理）方式、纯硬件的ASIC（专用集成芯片）或者FPGA（可编程逻辑门阵列）。 - Based on the dual-rail logic, a cascadable parallel binary logic gate was, proposed.
基于双轨逻辑，本文提出一种可级联的并行二值逻辑门。 - My paper design a Boolean logic gate by DNA computing.
本文就是利用DNA计算来设计布尔逻辑门。 - This paper introduces a new concept of implication logic function and implication logic gate. The implication logic gate can be used as a basic unit in a large-scale digital IC to simplify circuitry and reduce power dissipation.
本文引出蕴函逻辑函数和蕴函逻辑门的新概念，利用蕴函逻辑门作为大规模数字集成电路的基本单元可以简化电路，减小电路的功耗。 - Hermetically sealed, very high speed, logic gate optocoupler.
密封，非常高的速度，逻辑门光耦合器。 - Implication Logic Function and Implication Logic Gate
蕴函逻辑函数和蕴函逻辑门的研究 - Threshold Logic Gate ( TLG) is receiving much attention because of its logic versatility and functionally complete.
阈值逻辑门由于具有强大的逻辑功能且独自构成完备集而备受关注。 - This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
本文介绍了一种新的数码乘法器结构：采用一级逻辑门结构实现阵列式数码乘法器，并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。